PCB信号完整性设计指南 / Signal Integrity Design Guide for PCBs

Single-ended traces shall maintain plus or minus 10 percent impedance tolerance from target value. Differential pairs shall maintain plus or minus 10 percent differential impedance and plus or minus 5 percent intra-pair skew. Reference planes must be continuous beneath signal traces; splits or gaps in reference plane are prohibited within 3x trace width of signal path.

Minimum spacing between parallel traces shall be at least 3x trace width for signals with edge rates below 1ns. For high-speed signals above 1GHz use 5x trace width spacing or ground guard traces. Far-end crosstalk FEXT shall not exceed 5 percent of signal amplitude. Near-end crosstalk NEXT shall be evaluated for all adjacent nets.

Differential pairs shall be routed with constant spacing throughout the entire length. Length matching tolerance: plus or minus 5mil for signals above 5Gbps, plus or minus 10mil for 1-5Gbps. Avoid routing differential pairs over plane splits. When layer transition is necessary place ground vias within 1mm of signal vias.

Series termination resistor shall be placed within 5mm of driver output. Parallel termination required for bus topologies. AC termination recommended for DDR memory interfaces. Thevenin termination suitable for ECL logic. Termination resistor tolerance shall be plus or minus 1 percent for impedance-critical applications.

Eye diagram measurements shall verify signal integrity at receiver input. Minimum eye height: 60 percent of signal amplitude. Minimum eye width: 40 percent of unit interval. Jitter budget allocation: deterministic jitter at most 30 percent UI, random jitter at most 10 percent UI at BER 1E-12.