IPC-2222A establishes the generic performance requirements for the design of rigid printed boards. This standard covers single-sided, double-sided, and multilayer rigid PCB designs. It supplements IPC-2221 (Generic Standard on Printed Board Design) with specific requirements unique to rigid board technology. All design rules herein apply to rigid laminates including FR-4, polyimide, and other rigid substrate materials.

The layer stackup shall be designed to maintain symmetry about the centerline of the board to minimize warpage. For multilayer boards, signal layers should be paired with adjacent reference planes. The dielectric thickness between signal and reference layers shall be controlled to achieve target impedance. Minimum core thickness: 0.05 mm for inner layers. Prepreg thickness tolerance: ±10%. Recommended stackup sequence: Signal-Ground-Power-Signal for 4-layer; Signal-Ground-Signal-Power-Signal-Ground-Signal for 6-layer configurations.

Finished board thickness tolerance shall conform to Table 2-1. For boards ≤1.0 mm: tolerance ±0.10 mm. For boards 1.0-2.0 mm: tolerance ±0.15 mm. For boards >2.0 mm: tolerance ±0.20 mm. Thickness measurement shall be taken at least 12.7 mm from any board edge. Localized thinning due to copper removal in non-copper areas shall not exceed 10% of nominal thickness. Warpage shall not exceed 0.75% of board length or width for SMT boards, 1.5% for through-hole only boards.

The minimum annular ring for plated through-holes shall be determined by the formula: Annular Ring = (Pad Diameter - Hole Diameter) / 2. Minimum annular ring: 0.05 mm for Class 2, 0.075 mm for Class 3. The aspect ratio (board thickness to hole diameter) shall not exceed 10:1 for standard plating processes. For microvias, aspect ratio shall not exceed 1:1 per individual dielectric layer. Drill size tolerance: +0.05/-0.00 mm for PTH, ±0.025 mm for NPTH.

Thermal relief connections shall be used when connecting pads to internal power or ground planes to facilitate soldering and rework. Thermal relief shall consist of a minimum of four spokes connecting the pad to the plane copper. Spoke width: minimum 0.20 mm or 25% of pad diameter, whichever is greater. Gap between spoke and plane: minimum 0.15 mm. For high-current connections (>2A), direct connection to plane may be required with appropriate thermal management considerations. Thermal reliefs are not required for vias that serve as heat sinks.

Ground via stitching shall be implemented along board edges and around high-speed signal traces to provide return current paths and EMI shielding. Maximum spacing between ground vias: λ/20 at the highest operating frequency, or 2.5 mm, whichever is smaller. Ground vias shall be connected to the ground plane on every layer. Via diameter for stitching: minimum 0.3 mm finished hole size. Guard vias around sensitive signals shall be placed at intervals no greater than 3x the trace width. Via fence patterns shall form a continuous shield around RF sections.

Minimum conductor width and spacing shall be determined by voltage, current carrying capacity, and manufacturing capability. For external layers: minimum trace width 0.10 mm (Class 2), 0.125 mm (Class 3). For internal layers: minimum trace width 0.075 mm (Class 2), 0.10 mm (Class 3). Minimum spacing between conductors: 0.10 mm for voltages ≤50V, increasing per Table 4-1 for higher voltages. Conductor width tolerance: ±20% of nominal for etched traces. Copper weight selection: 1 oz (35μm) standard, 2 oz (70μm) for high current, 0.5 oz (17.5μm) for fine-pitch designs.

Controlled impedance traces shall be designed using field solver calculations accounting for actual dielectric constant, trace geometry, and reference plane proximity. Single-ended impedance tolerance: ±10% of target value (±5% recommended for high-speed). Differential impedance tolerance: ±10% of target. Reference plane must be continuous beneath impedance-controlled traces; no splits or cutouts allowed within 3x trace width of the controlled trace. Dielectric constant (Dk) variation across laminate: maximum ±0.2 for impedance-critical layers. Test coupon shall be included on production panel for impedance verification.

Copper foil thickness shall be specified in ounces per square foot (oz/ft²) or micrometers (μm). Standard weights: 0.5 oz (17.5 μm), 1 oz (35 μm), 2 oz (70 μm), 3 oz (105 μm). Base copper thickness tolerance per IPC-4562. Plated copper thickness after processing: minimum 20 μm for barrel plating in PTH. Surface copper thickness after plating shall account for both base foil and plating buildup. For embedded resistor/capacitor layers, use specialized copper-clad materials per manufacturer specification.

Surface finish shall be selected based on shelf life, solderability, wire bonding, and contact requirements. Acceptable finishes include: HASL (Hot Air Solder Leveling) - shelf life 12 months; ENIG (Electroless Nickel Immersion Gold) - shelf life 12 months, suitable for BGA; OSP (Organic Solderability Preservative) - shelf life 6 months; Immersion Silver - shelf life 6 months; Immersion Tin - shelf life 6 months; ENEPIG - shelf life 12 months, suitable for wire bonding. Finish thickness requirements per IPC-4552 (ENIG), IPC-4553 (Immersion Silver), IPC-4554 (Immersion Tin).

Solder mask shall be applied to both sides of the board except where component attachment or electrical contact is required. Solder mask opening tolerance: +0.05/-0.00 mm relative to pad size for SMD pads. Solder mask bridge between adjacent pads: minimum 0.10 mm for 0.5 mm pitch, 0.075 mm for 0.4 mm pitch. Solder mask thickness: 10-35 μm over copper, minimum 5 μm over conductor edges. Solder mask shall extend beyond pad edges by minimum 0.05 mm (dam) to prevent solder bridging. Tenting of vias: fully tented, partially tented, or open per design specification.

Silkscreen legend shall identify components, polarity, test points, and board identification. Minimum silkscreen line width: 0.15 mm. Minimum silkscreen text height: 1.0 mm (recommended 1.27 mm for readability). Silkscreen shall not overlap exposed copper or solder mask openings. Component reference designators shall be visible after assembly. Polarity markings required for: diodes, capacitors, ICs, connectors. Board identification: part number, revision level, date code, manufacturer logo. Silkscreen ink color: white (standard), yellow, black per customer specification.

Test points shall be provided for all critical nets to enable in-circuit testing (ICT) and functional verification. Minimum test point diameter: 1.0 mm for ICT probe access, 0.5 mm for flying probe. Test point spacing: minimum 2.5 mm center-to-center for ICT fixtures. Test points shall be located on one side of the board preferably; if both sides required, fixture cost increases. Test points must have exposed copper with solder mask opening. Dedicated test pads preferred over using component pads. Net coverage: 100% of nets shall have at least one accessible test point.

Panelization shall optimize manufacturing yield and assembly compatibility. Panel size shall match fabrication equipment capabilities (standard: 457×610 mm, 508×610 mm). Routing tab (mouse bite) dimensions: minimum 3 mm wide, 0.5 mm thick neck. V-score depth: 1/3 of board thickness from each side, residual web: 1/3 of thickness. Tooling holes: minimum 3.175 mm diameter, located at panel corners and center. Fiducial marks: minimum 1.0 mm diameter, placed at panel corners and individual board corners for SMT alignment. Breakaway rails: minimum 5 mm width for conveyor transport.

Electrical clearance (air gap) and creepage (surface distance) shall meet safety requirements per application class. For uncoated boards at sea level: 50V requires 0.1 mm clearance; 100V requires 0.25 mm; 250V requires 0.8 mm; 500V requires 1.5 mm. Conformal coating reduces required clearance by up to 50%. Creepage distance shall account for pollution degree and material group (CTI value). Slots and cutouts may be used to increase creepage path. High-voltage isolation barriers require reinforced insulation per IEC 60950-1 or IEC 62368-1.

Conductor current carrying capacity shall be calculated per IPC-2221 Section 6.2 using temperature rise criteria. External layer: 1 oz copper, 10 mil trace carries approximately 1A at 10°C rise. Internal layer: derate external capacity by factor of 0.5 due to reduced heat dissipation. For currents exceeding single trace capacity, use multiple parallel traces or increase copper weight. Via current capacity: single 0.3 mm via ≈ 0.5A; use via arrays for higher currents. Fuse traces shall be designed with controlled neck-down geometry for predictable fusing characteristics.

Mounting hole clearance: minimum 0.5 mm from hole edge to nearest copper. Board outline tolerance: ±0.10 mm for routed edges, ±0.15 mm for scored edges. Corner radius: minimum 0.5 mm for internal corners to reduce stress concentration. Cutout and slot tolerance: ±0.10 mm. Edge connector finger alignment: ±0.05 mm from board edge. Chamfer or radius required on board corners: minimum 0.5 mm. Keep-out zone from board edge: minimum 1.0 mm for routing, 2.0 mm for V-score panels. Component placement keep-out from bend lines: minimum 5 mm.

Laminate material shall be selected based on Tg, Td, CTE, Dk, Df, and moisture absorption requirements. Standard FR-4: Tg ≥130°C (mid-Tg) or ≥170°C (high-Tg). High-frequency applications: low-Dk/Df materials (Rogers, Megtron, Nelco). Halogen-free requirement: per IPC-4101B. UL flammability rating: minimum V-0 for most applications. Moisture absorption: maximum 0.5% for standard FR-4. CAF (Conductive Anodic Filament) resistance required for high-reliability designs with tight via spacing. Material qualification per IPC-4101 slash sheet specification.