中英双语 · 工程师回复

PCB 问答社区

工艺难题发出来，认证工厂工程师为你解答

我要提问

4 个问题

4层板做 50Ω 单端阻抗，介质用 7628 半固化片压合后实际阻抗偏低 3Ω 左右，应该怎么调整？

硬件工程师_陈2026-10-15中文

精创电路-工艺部认证工程师2026-10-15

压合后介质厚度会比理论值薄 10% 左右，建议按实际叠层参数重新仿真：可将线宽从 6.5mil 收窄到 6mil，或要求板厂按阻抗条实测数据调整蚀刻补偿。下单时注明阻抗公差 ±7% 并附阻抗要求表。

Layout老王2026-10-16

补充一点：7628 树脂流动量大，层压结构对称性也会影响，建议和板厂确认他们的压合参数表。

沉金板存放了 8 个月还没贴片，可焊性会不会有问题？需要烘烤吗？

采购_李女士2026-10-12中文

华新电子-品质部认证工程师2026-10-12

ENIG 沉金板真空包装未开封的情况下保存期一般 12 个月，8 个月通常仍可正常使用。若包装破损或环境湿度大，建议贴片前 120℃ 烘烤 4 小时，并先做可焊性测试确认。

What is the minimum annular ring you recommend for a 6-layer board with 0.25mm mechanical vias? We had two pads lifted in the last prototype run.

RF_Design_Tom2026-10-10EN

Hengtong-Engineering认证工程师2026-10-11

For 0.25mm (10mil) drilled vias, keep the pad at 0.5mm minimum (annular ring ≥0.125mm per side). Pad lifting usually comes from drill-to-copper misregistration; ask your fab for their drill tolerance (typically ±0.075mm) and add 0.05mm extra ring margin for prototypes.

Is back-drilling necessary for 10Gbps SerDes traces on a 12-layer board, or can we live with via stubs at 0.8mm board thickness?

SI_Engineer_Amy2026-10-08EN

Jingchuang-Engineering认证工程师2026-10-09

At 10Gbps (Nyquist ~5GHz), a via stub of several hundred microns acts as a quarter-wave resonator and can cause noticeable insertion loss dips. For a 12-layer 0.8mm board we recommend back-drilling with 0.2mm stub tolerance, or restructure the stackup so signal layers sit closer to the drill entry side.